Electronic memory having impedance-matched sensing
US7126853B2 · kind B2 · utility
11Cited by
8References
48Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 14, 2003 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Nov 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic memory, typically a flash EPROM, contains an array of memory sections (40), each containing an array of memory cells (54). Global bit lines (60) fully traverse the memory. Local bit lines (58) partially traverse the memory. Data stored in the memory is sensed with an arrangement that utilizes impedance matching to achieve high sensing accuracy with low noise sensitivity. The impedance matching may be provided solely from the sections and lines of the memory or partially from a separate reference memory section (102) that contains reference memory cells (104).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.