Technique for programming floating-gate transistor used in circuitry as flash EPROM
US7126854B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 17, 2004 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Jun 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The sequence in which the voltages (VSL, VDL, VSG, and VCL) applied to the source/drain regions (S and D), select gate (SG), and (if present) control gate (CG) of a floating-gate field-effect transistor (20) start to change value during a programming operation is controlled so as to avoid adjusting the transistor's programmable threshold voltage toward a programmed value when the transistor is intended to remain in the erased condition, i.e., not go into the programmed condition. With the voltage (VSL) at one source/drain region (S) changing from a nominal value to a programming value, the sequence entails causing the voltage (SG) at the select gate to start changing from a nominal value to a programming-enable value after the voltage at the other source/drain region (D) starts changing from a nominal value to a programming-inhibit value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.