Low power ROM architecture
US7126866B1 · kind B1 · utility
4Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2002 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Oct 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a ROM structure, power consumption is reduced by providing for pre-discharging of only the bit line corresponding to the memory location that is being read. Column select lines are coupled to logic to switch in a pre-discharging circuit prior to reading, and to disconnect, from the pre-discharging circuit during reading, only the bit line corresponding to the memory location being read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.