Method for manufacturing a semiconductor device having a low junction leakage current
US7129141B2 · kind B2 · utility
2Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2004 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Dec 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0335
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a DRAM device includes the step of implanting phosphor at a specified dosage and heat treating the implanted phosphor for diffusion thereof to form source/drain regions, and implanting fluorine into the source/drain regions and heat treating the implanted fluorine for diffusion thereof. The resultant DRAM memory cell has a larger data storage capability due to lower junction leakage current caused by vacancy type defects formed in the metallurgical junction between the source/drain regions and the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.