Method and structure to improve reliability of copper interconnects
US7129165B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2004 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | Jun 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a conductor structure on a surface of a wafer is provided. The surface of the wafer includes cavities separated by field regions. Initially, a barrier layer is deposited on the surface that includes cavities separated by field regions. A thin seed layer with a substantially uniform thickness is deposited on the barrier layer. The barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity. The remaining volume of each cavity is filled with a conductive material which is formed on the seed layer. The conductive layer has a substantially small thickness. After forming the conductive layer, the wafer is annealed to increase grain size in the conductive layer and the seed layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.