Reducing defect formation within an etched semiconductor topography

US7129178B1 · kind B1 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Benjamin Schwarz · Strohberg, DE
• Chan Lon Yan · Los Gatos, US
• Hanna Bamnolker · Cupertino, US
• Daniel Arnzen · Eden Prairie, US

Key dates

• Filing date: Feb 13, 2002
• Grant date: Oct 31, 2006
• Expiry date: Jul 9, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32137
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an etched portion of the semiconductor topography. Such defects may include bilayer mounds of nitride and a material comprising silicon, for example. In some embodiments, the method may include etching a stack of layers within a single etch chamber. The stack of layers may include, for example, a nitride layer interposed between an anti-reflective layer and an underlying layer. In addition, the single etch chamber may be a plasma etch chamber designed to etch materials comprising silicon. As such, the method may include etching an anti-reflective layer in a plasma etch chamber designed to etch materials comprising silicon.