Semiconductor circuit arrangement with trench isolation and fabrication method

US7129540B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Achim Gratz · Dresden, DE
• Klaus Knobloch · Radeberg, DE
• Franz Schuler · Kreßbronn, DE

Key dates

• Filing date: Feb 12, 2004
• Grant date: Oct 31, 2006
• Expiry date: Feb 12, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/685

Abstract

An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insulating function between adjacent components, the patterning of the charge-storing layer and also the subdivision of doping layers of the semiconductor layer (14).