Interleaved mirrored memory systems
US7130229B2 · kind B2 · utility
24Cited by
28References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2002 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | May 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a system includes a first memory assembly coupled to a first channel and a second memory assembly coupled to a second channel. The system includes a memory controller to write first and second primary data sections to the first and second memory assemblies, respectively, and write first and second redundant data sections to the second and first memory assemblies, respectively, wherein the first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.