Generating fast logic simulation models for a PLD design description
US7131091B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2004 |
| Grant date | Oct 31, 2006 |
| Priority date | — |
| Expiry date | May 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various approaches for generating a clock accurate simulation model from a circuit design description are disclosed. In one approach, a graph representation of the circuit design description is created. The graph representation includes nodes and edges. From the nodes in the graph representation, a plurality of register nodes are generated to correspond to respective register functions. Logic optimization is performed on nodes that represent combinational logic functions. For each register node and each output node, an evaluation equation is generated after performing logic optimization. For each clock cycle of a logic simulation, each evaluation equation is evaluated and produces an output value for the next clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.