Method and apparatus for forming a memory structure having an electron affinity region
US7132336B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2002 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Jun 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28185
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom portion of the dielectric region. This doped region includes a suitable electron affinity material. A gate electrode is connected with the top of the dielectric region. In some embodiments, suitable electron affinity materials are introduced into the doped region using implantation techniques. In another embodiment, the electron affinity material is introduced into the doped region using plasma treatment of the dielectric region and the redeposition of additional dielectric material on top of the dielectric region and doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.