Application of post-pattern resist trim for reducing pocket-shadowing in SRAMs
US7132340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Dec 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods (600, 700) are disclosed for minimizing the effect of pocket shadowing in the fabrication of an angled pocket implant (32) extending underlying a gate region (21) of a transistor (10), particularly in SRAM devices (400). The pocket shadowing is minimized by initially forming a relatively thick resist layer (810) overlying the semiconductor device (800), then the resist layer thickness (810y) is reduced (trimmed) to a reduced thickness (860y) by using a subsequent post-development dry or wet resist-reduction etch process (630, 730). The etch process (630, 730) also increases corner rounding (860r), thereby reducing pocket shadowing of the angled implant from nearby features or the resist (228, 328, 860). The pocket shadow reduction may be accomplished by first forming (610, 710) the relatively thick resist layer (810) overlying the semiconductor device (400, 800). The resist layer (860) is then wet and/or dry etched (630, 730) to trim the resist thickness (860y) and to round the corners (860r) of the resist (442, 860). In combination, these changes reduce shadowing of angled implants from nearby structures and resist edges. The method may further comprise a first implant (72…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.