Method of reducing fringing capacitance in a MOSFET
US7132342B1 · kind B1 · utility
17Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Dec 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
Abstract
In a method of reducing the fringing capacitance of a MOSFET, the nitride spacers on the sides of the MOSFET gate are etched away to form trenches, which are plugged to define air spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.