SiGe layer having small poly grains
US7132700B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Aug 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0109
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A disclosed embodiment is a method for fabricating a structure in a semiconductor die, the method comprising depositing a silicon buffer layer over a single crystalline region and at least one isolation region at a first pressure, where the silicon buffer layer is continuous, i.e. comprises small poly grains, over the at least one isolation region. The method further includes forming a silicon germanium layer over the silicon buffer layer at a second pressure, where the silicon germanium layer is also continuous, i.e. comprises small poly grains, over the at least one isolation region. In one embodiment, the first pressure is less than the second pressure. In other embodiments, a structure is fabricated according to the above method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.