Controllable conduction device with electrostatic barrier
US7132713B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2002 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Apr 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.