Data path configurable for multiple clocking arrangements
US7132854B1 · kind B1 · utility
9Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Dec 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data path (200) can be configured to accommodate different clocking arrangements. In one mode, data values may be output at a single data rate: one data value every clock cycle. In another mode, data values may be output at a double data rate: two data values every clock cycle. A data path (200) can be compact circuit structure, needing only an additional mode multiplexer (206) and inverter over a conventional D-type master-slave flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.