Method and apparatus for glitch-free control of a delay-locked loop in a network device
US7132866B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | May 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals is within specified tolerances, producing a correction signal when the required phase difference between the received clock and reference clock signals is not within the specified tolerances, utilizing the correction signal to change a delay setting and forwarding the correction signal to slave DLL modules in communication with the DLL module. The comparing, producing, utilizing and forwarding steps are performed only after a period of time has elapsed from a prior incidence of the comparing, producing, utilizing and forwarding steps, where the period of time is sufficient to allow the DLL to settle and no extraneous results are produced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.