Method and apparatus for avoiding gated diode breakdown in transistor circuits
US7132873B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2003 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | May 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
An N-channel transistor protection circuit and method are disclosed that prevent gated diode breakdown in N-channel transistors that have a high voltage on their drain. The disclosed N-channel protection circuit may be switched in a high voltage mode between a high voltage level and a lower rail voltage. A high voltage conversion circuit prevents gated diode breakdown in N-channel transistors by dividing the high voltage across two N-channel transistors, MXU0 and MXU1, such that no transistor exceeds the breakdown voltage, Vbreakdown. An intermediate voltage drives the top N-channel transistor, MXU0. The top N-channel transistor, MXU0, is gated with a voltage level that is at least one N-channel threshold, Vtn, below the high voltage level, Vep, using the intermediate voltage level, nprot. The drain voltage of MXU0 will be at least one N-channel threshold, Vtn, lower than the input voltage level, nprot, and the drain voltage Vd of the bottom N-channel transistor, MXU1, is limited to less than the breakdown voltage, Vbreakdown.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.