Shane Hollmer
91Patents
26h-index
58Co-inventors
91Inventor score
Filing activity: Dec 1, 1993 → Jul 2, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5995417A | Scheme for page erase and erase verify in a non-volatile memory array | Physics | 236 | Expired |
| US6215702A | Method of maintaining constant erasing speeds for non-volatile memory cells | Physics | 165 | Expired |
| US6222768A | Auto adjusting window placement scheme for an NROM virtual ground array | Physics | 160 | Expired |
| US6009014A | Erase verify scheme for NAND flash | Physics | 155 | Expired |
| US6201737A | Apparatus and method to characterize the threshold distribution in an NROM virtual ground array | Physics | 129 | Expired |
| US6175523A | Precharging mechanism and method for NAND-based flash memory devices | Physics | 125 | Expired |
| US6275414A | Uniform bitline strapping of a non-volatile memory cell | Electricity | 111 | Expired |
| US5821800A | High-voltage CMOS level shifter | Electricity | 105 | Expired |
| US5828601A | Programmed reference | Physics | 96 | Expired |
| US6240020A | Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices | Physics | 91 | Expired |
| US6272043A | Apparatus and method of direct current sensing from source side in a virtual ground array | Physics | 86 | Expired |
| US6510082B1 | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold | Physics | 67 | Expired |
| US6504757B1 | Double boosting scheme for NAND to improve program inhibit characteristics | Physics | 64 | Expired |
| US6181605A | Global erase/program verification apparatus and method | Physics | 50 | Expired |
| US6583479B1 | Sidewall NROM and method of manufacture thereof for non-volatile memory cells | Electricity | 49 | Expired |
| US5511026A | Boosted and regulated gate power supply with reference tracking for multi-density and low voltage supply memories | Physics | 48 | Expired |
| US5638326A | Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device | Physics | 46 | Expired |
| US7132873B2 | Method and apparatus for avoiding gated diode breakdown in transistor circuits | Electricity | 46 | Expired |
| US5973546A | Charge pump circuit architecture | Electricity | 41 | Expired |
| US8331128B1 | Reconfigurable memory arrays having programmable impedance elements and corresponding methods | Physics | 40 | Active |
| US6262469A | Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor | Electricity | 39 | Expired |
| US6538270B1 | Staggered bitline strapping of a non-volatile memory cell | Electricity | 37 | Expired |
| US6593606B1 | Staggered bitline strapping of a non-volatile memory cell | Electricity | 35 | Expired |
| US6269025A | Memory system having a program and erase voltage modifier | Physics | 30 | Expired |
| US5978267A | Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same | Physics | 30 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.