Method for adaptive critical path delay estimation during timing-driven placement for hierarchical programmable logic devices
US7133819B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 2001 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | May 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a method for estimating delay data comprising receiving an electronic representation of a source electronic design, estimating the criticality of connections which have not yet been placed across a boundary based on statistical data received from at least one other design and revising the design in a manner that biases the design towards a state in which connections with the highest criticality have their delays minimized. A statistical estimate is generated for uncut connections on a path in a partially placed source design comprising receiving at least one source design, partitioning the design, and generating statistical data corresponding to each type of partitioning cut.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.