Scalable I/O signaling topology using source-calibrated reference voltages
US7133945B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | May 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/028
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention is a scalable I/O interface signaling technology for improved communication between semiconductor devices. In one embodiment, a system contains a first semiconductor device that includes a first characterization mechanism, a control logic coupled to the first characterization mechanism, a voltage generating mechanism coupled to the control logic and a transmit buffer. The control logic adjusts at least a first voltage generated by the voltage generating mechanism based on at least a value determined by the first characterization mechanism. The first voltage is coupled to the transmit buffer to define at least a transmit voltage signal level. In an alternate embodiment, the first voltage is coupled to a receive buffer in a second semiconductor device to define at least a receive voltage signal level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.