Prioritized bus request scheduling mechanism for processing devices
US7133981B2 · kind B2 · utility
4Cited by
16References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2004 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Jan 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scheduler stores data to be scheduled. The scheduler may include an array that identifies relative priorities among the queue entries according to a first priority scheme, such as by age. The scheduler also may include a priority register array identifying relative priorities among the queue entries according to a second priority scheme, such as by data type. A plurality of detectors coupled to the array and to the priority register array may determine which data is to be scheduled next.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.