Processing device for buffering sequential and target sequences and target address information for multiple branch instructions
US7134004B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2000 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Oct 7, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.