Map compiler pipelined loop structure
US7134120B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2003 |
| Grant date | Nov 7, 2006 |
| Priority date | — |
| Expiry date | Jun 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/447
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, a loop valid node coupled to the loop body that determines a final loop iteration, and an output value storage node coupled to the circulate node, where the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred. Also, a control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, and a loop driver node coupled to the circulate node, where the loop driver node sets a period for each iteration of the loop body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.