Fluxless bumping process
US7134199B2 · kind B2 · utility
6Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2002 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Oct 27, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49179
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.