Reduced footprint tool for automated processing of microelectronic substrates
US7134827B2 · kind B2 · utility
3Cited by
24References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Sep 28, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/141
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides tools and methods of processing microelectronic substrates in which the tools maintain high throughput yet have dramatically lower footprint than conventional tools. In preferred aspects, the present invention provides novel tool designs in which multiple tool functions are overlapped in the x, y, and/or z axes of the tool in novel ways.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.