Design-based monitoring
US7135344B2 · kind B2 · utility
47Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | May 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.