Line edge roughness reduction
US7135419B2 · kind B2 · utility
5Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Nov 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0273
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A base-loaded polymer is applied to a semiconductor feature formed after exposing and developing a photoresist layer in order to reduce line edge roughness caused by a residual acid collecting on the edges of the feature during the post-exposure bake of the photoresist. Alternatively, a polymer is applied containing grains that are of suitable for smoothing the line edge roughness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.