Structure and method for making strained channel field effect transistor using sacrificial spacer
US7135724B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 29, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Oct 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.