Semiconductor device having self-aligned contact hole and method of fabricating the same
US7135744B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 3, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Mar 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns and the gate pattern are covered with word line spacers and gate spacers having the same width as that of the word line spacers, respectively. The semiconductor substrate having the word line spacers and the gate spacers is covered with an interlayer insulating layer. A self-aligned contact hole formed in the interlayer insulating layer penetrates a predetermined region between the word line patterns. The self-aligned contact hole is formed by etching the interlayer insulating layer and the word line spacers. The side walls of the self-aligned contact hole are covered with a self-aligned contact spacer having a width different from that of the gate spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.