Individualized low parasitic power distribution lines deposited over active integrated circuits
US7135759B2 · kind B2 · utility
13Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2001 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Jul 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 mΩ/□ and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.