Patent · US Expired

Integrated circuit chip utilizing carbon nanotube composite interconnection vias

US7135773B2 · kind B2 · utility

24Cited by
0References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 26, 2004
Grant dateNov 14, 2006
Priority date
Expiry dateFeb 26, 2024

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY10S977/842
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.