System and method for reducing skew in complementary signals that can be used to synchronously clock a double data rate output
US7135899B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Jun 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A circuit, system, and method are provided for generating edge-aligned, complementary output signals from complementary input signals. The output and input signals can, according to one example, be clock signals. The circuit, system, and method can use the rising edges of the complementary pair of input signals to trigger transitions on the complementary pair of output signals. More specifically, the rising edge of a true input clock signal will trigger the rising edge of the true output clock signal and the falling edge of the inverted output clock signal. A rising edge of the inverted input clock signal will trigger the falling edge of the true output clock signal, and the rising edge of the inverted output clock signal. Moreover, the circuit, system, and method ensures that at any time only one transition occurs on the active inputs of a final logic stage of the clock generation circuit. Also, the circuit, system, and method support double data rate (DDR) data and echo clock generation, where the echo clock transitions in sync with the DDR output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.