Phase jumping locked loop circuit
US7135903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2003 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Feb 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.