Single bit nonvolatile memory cell and methods for programming and erasing thereof
US7136306B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2003 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Mar 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming a single bit nonvolatile memory cell integrated on a metal-dielectric-semiconductor technology chip. The memory cell comprises a semiconductor substrate including a source, a drain, and a channel in-between the source and the drain. The memory cell further comprises a control gate that comprises a gate electrode and a dielectric stack. The gate electrode is separated from the channel by the dielectric stack. Further, the dielectric stack comprises at least one charge storage dielectric layer. The method for programming the memory cell comprises applying electrical ground to the source, applying a first voltage having a first polarity to the drain, applying a second voltage of the first polarity to the control gate; and applying a third voltage having a second polarity opposite to the first polarity to the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.