DRAM with self-resetting data path for reduced power consumption
US7136317B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2005 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Aug 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access memory (RAM), such as a dynamic RAM (DRAM) or embedded DRAM (eDRAM) on a CMOS integrated circuit (IC) logic chip. Memory banks drive one line of a connected global data line pair to develop a difference signal on the pair. Simultaneously, a global signal monitor line discharges to develop a signal that mirrors the signal developing on one of the pair. When the global signal monitor line discharges sufficiently to indicate that the difference signal is large enough to sense, a global sense control sets a global data sense amplifier, the memory banks drive shuts off, and the global sense control initiates restoring global data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.