Methods and apparatus for minimizing current surges during integrated circuit testing
US7137052B2 · kind B2 · utility
0Cited by
12References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 19, 2001 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Oct 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Structural testing can lead to high and abnormal current surges. Disclosed herein are methods for designing and testing an IC so that current surges therein may be minimized while the IC is being tested. One disclosed way to minimize current surges is by gating out shift induced node state transitions. Another disclosed way to minimize current surges is to operate two or more of an IC's scan chains in parallel, but out-of-phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.