Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory
US7137055B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 16, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Jul 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.