Assertion checking using two or more cores
US7137086B2 · kind B2 · utility
22Cited by
3References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Mar 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318533
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An SoCs with functionally reconfigurable modules employing the modules to configure circuitry for performing assertion checking. Both at-speed assertion checking as well as continuous single step (CSS) assertion checking is disclosed. Advantageously, the checking of the various cores within the SoC is carried out concurrently, in subsets of the entire set of assertions that need to be checked out. Advantageously, bit extraction and injection is used in CSS assertion checking to permit use of relatively small registers for the assertion checking of each subset of assertions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.