Wafer level packaging technique for microdevices
US7138293B2 · kind B2 · utility
30Cited by
0References
55Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2002 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Mar 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16235
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method is disclosed for fabricating a integrated device, such as a MEMS device. A first wafer is provided on an exposed surface with a layer of gold, gold alloy or gold compound. A second wafer is provided on its exposed surface with under-layer of gold, gold alloy or gold compound; and an over- of bismuth, bismuth alloy, a compound of bismuth, cadmium, cadmium alloy, a compound of cadmium compound, tin, tin alloy, or a compound of tin. The wafers are then brought into contact and bonded at their surfaces through the deposited layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.