Semiconductor memory device
US7138674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2003 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Feb 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a cell block composed of several series-connected units having a ferroelectric capacitor and a cell transistor parallel-connected to the ferroelectric capacitor and a select transistor connected to an end of the cell block. Mutually separated first impurity diffusion layers are formed on the surface of the semiconductor substrate along a first direction, and have a first area. A second impurity diffusion layer is formed on the surface of the semiconductor substrate separated from the end first impurity diffusion layer, and has a second area. A first gate electrode is provided on the semiconductor substrate between the first impurity diffusion layers along a second direction. A second gate electrode is provided on the semiconductor substrate between the end first impurity diffusion layer and the second impurity diffusion layer along a second direction. A contact electrically connects a bit line and the second impurity diffusion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.