Memory device with floating gate stack
US7138680B2 · kind B2 · utility
25Cited by
11References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2004 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Sep 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a substrate including isolation regions and active regions, and a floating gate stack proximate the substrate. The floating gate stack comprises a first high-k dielectric layer proximate the substrate, a first metal layer proximate the first high-k dielectric layer, and a second high-k dielectric layer proximate the first metal layer. The memory device comprises a control gate electrode proximate the floating gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.