Vertical MOSFET SRAM cell
US7138685B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2002 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Aug 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.