Method and system for testing a dual-port memory at speed in a stressed environment
US7139204B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 6, 2005 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Jun 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for testing a multi-port memory cell are described. According to one embodiment of the invention, a multi-port memory device comprises an array of multi-port memory cells. Accordingly, each multi-port memory cell is connected to one word-line and two bit-lines per read/write port. The memory device includes memory testing logic to perform a first memory access operation (e.g., read/write) at a first port of the multi-port memory cell while the memory cell is in a stressed condition. For example, the first memory access operation occurs while a second memory access operation is emulated on a second port. Moreover, the memory access operations occur at a frequency that is substantially equivalent to a maximum operating frequency of the dual-port memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.