Memory component with improved noise insensitivity
US7139206B2 · kind B2 · utility
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6References
16Claims
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Assignee
Inventor
Key dates
| Filing date | Jan 7, 2005 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Jan 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory component comprises a memory cell array, signal inputs, input amplifiers connected to respective ones of the signal inputs, for receiving, amplifying and outputting data, address or control signals, a data, address or control signal generator for the memory cell array, a first supply network for supplying power to the input amplifiers and a second supply network for supplying power to the data, address or control signal generator, wherein the first supply network and the second supply network do not have a direct connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.