On chip network with independent logical and physical layers
US7139860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2002 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Oct 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket includes a processor element interface and a port interface. Each processor element interface of at least two bus gaskets operates according to a first logical layer protocol. Each port interface operates according to a consistent port interface protocol by sending transaction requests and receiving acknowledgements and by sending and receiving packet datums via the corresponding port. The physical layer interface transfers packets between the ports and includes an arbiter and an interconnect coupled to each port. Additional bus gaskets may be added that operate according to a second logical layer protocol which may or may not be compatible with the first. Any bus gasket may be added that is configured to communicate using multiple logical layer protocols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.