Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability
US7139944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2003 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | May 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.