Automatic self test of an integrated circuit component via AC I/O loopback
US7139957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2003 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Dec 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31853
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.