Integration of a run-time parameterizable core with a static circuit design
US7139995B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2002 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Nov 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for integrating a run-time parameterizable logic core with a static circuit design. A configuration bitstream is generated from a main circuit design that is specified in a hardware description language. The main circuit design includes a first sub-circuit design that specifies a selected subset of resources of the PLD needed by the RTP core and an interface between the RTP core and other parts of the main circuit design. Via execution of a run-time reconfiguration control program, the configuration data that correspond to the first sub-circuit design are replaced with configuration data that implement the RTP core. The run-time reconfiguration program then configures the PLD with the updated configuration bitstream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.