Method to manufacture LDMOS transistors with improved threshold voltage control
US7141455B2 · kind B2 · utility
8Cited by
13References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 12, 2003 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Apr 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.