Method of fabricating nano-scale resistance cross-point memory array
US7141481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Dec 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.